An E cient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers

In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers LFSRs The same LFSR that is used to gen erate pseudo random patterns is loaded with seeds from which it produces vectors that cover the testcubes of dif cult to test faults The scheme is compatible with scan design and achieves full coverage as it is based on random patterns combined with a deterministic test set A method for processing the test set to allow for e cient encoding by the scheme is described Algorithms for calculating LFSR seeds from the test set and for the selection and ordering of polynomials are described Experimental results are pro vided for ISCAS benchmark circuits to demonstrate the e ectiveness of the scheme The scheme allows an excel lent trade o between test data storage and test application time number of test patterns with a very small hardware overhead We show the trade o between test data storage and number of test patterns under the scheme